This invention relates to methods of manufacturing a semiconductor power device having a source region formed using a sidewall extension of an upstanding gate structure, particularly, but not exclusively, comprising a trench-gate. The device may be, for example, an insulated-gate field-effect power transistor (hereinafter termed MOSFET) or an insulated-gate bipolar transistor (hereinafter termed IGBT). The invention also relates to semiconductor devices manufactured by such a method.
In manufacturing a trench-gate power device by a method as disclosed in United States patent specification U.S. Pat. No. 5,378,655 (our reference PHB 33836), an upstanding gate structure is formed at a major surface of a semiconductor body, and a sidewall extension (also termed a "spacer") is provided at upstanding sides of the gate structure to form a step with an adjacent surface area of a body region of a first conductivity type. The body region of the first conductivity type extends adjacent to the gate structure to provide the device with a channel-accommodating portion, to which the gate is capacitively coupled. In one embodiment, the sidewall extension comprises doped semiconductor material of opposite, second conductivity type which is separated from the gate by insulating material and which provides a source region of the device. The channel-accommodating portion forms a p-n junction with the source region. A source electrode is deposited over the step so as to contact the doped semiconductor material of the sidewall extension and the adjacent surface area of the first conductivity type.
In this method of U.S. Pat. No. 5,378,655 the source region is self-aligned with the trench-gate, by means of the spacers. Two types of embodiment are disclosed. In the first type, the initially-formed spacer is an etchant mask on part of a surface region of the second conductivity type in the body, and exposed areas of the surface region are then etched away to leave a remaining portion of the second conductivity type under the mask as the source region. In the second type, the spacer is of doped material (for example, doped polycrystalline silicon, or a doped oxide or glass) and serves as a dopant diffusion source for diffusing the dopant of the second conductivity type into the semiconductor body to form the source region.
United States patent specification U.S. Pat. No. 5,665,619 discloses a different trench-gate device process in which a spacer (sidewall extension) of insulating material (undoped oxide) is provided on part of a previously-formed source region so as to define a contact window that is self-aligned to the upstanding insulated trench-gate structure. A high-doped portion is then formed in the body by a blanket implant of dopant of the first conductivity type. This high-doped portion has a doping concentration of said first conductivity type which is higher than that of the channel-accommodating portion but lower than the conductivity-determining dopant concentration of the source region. The source region overdopes the ends of the high-doped portion which extends to a shallower depth in the body than the p-n junction between the source region and the channel-accommodating portion of the body region. At the self-aligned contact window, the source electrode contacts the high-doped portion of the body region of the first conductivity type and the adjacent surface area of the source region of the second conductivity type. No such separately-provided high-doped portion of the body region is described in the devices disclosed in U.S. Pat. No. 5,378,655. The whole contents of both U.S. Pat. No. 5,378,655 and U.S. Pat. No. 5,665,619 are hereby incorporated herein as reference material.